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THE READ TESTBENCH IN CADENCE — PRECHARGED BITLINE INTO THE CELL AT 180 mV.

Many modern industries (e.g., medical, power, shipping) are becoming increasingly reliant on low-power, local computing resources. Subthreshold logic can allow for lower power use where the associated drop in speed is acceptable. Reducing the VDD of both logic and memory can reduce dynamic energy usage with the square of voltage reduction. However, such an approach is not typically feasible with standard 6T SRAM designs, due to primarily a combination of the reduction in noise margins and array-wide process variation. This paper examines the theory of subthreshold SRAM, implements an approach proposed by Zhai et al. (2008), and compares this against a standard 6T SRAM cell.

5 PAGES · SCHEMATICS, TESTBENCHES, BUTTERFLY CURVES, AND WRITE TRANSIENTS.